1. Field of the Invention
The present invention relates to technology for non-volatile memory.
2. Description of the Related Art
Semiconductor memory devices have become more popular for use in various electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other devices. Electrical Erasable Programmable Read Only Memory (EEPROM) and flash memory are among the most popular non-volatile semiconductor memories.
Both EEPROM and flash memory utilize a floating gate that is positioned above and insulated from a channel region in a semiconductor substrate. The floating gate is positioned between source and drain regions. A control gate is provided over and insulated from the floating gate. The threshold voltage of the transistor is controlled by the amount of charge that is retained on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate before the transistor is turned on to permit conduction between its source and drain is controlled by the level of charge on the floating gate.
When programming an EEPROM or flash memory device, such as a NAND flash memory device, typically a program voltage is applied to the control gate and the bit line is grounded. Electrons from the channel are injected into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the memory cell is raised so that the memory cell is in a programmed state. More information about programming can be found in U.S. patent application Ser. No. 10/379,608, titled “Self Boosting Technique,” filed on Mar. 5, 2003; U.S. patent application Ser. No. 10/629,068, titled “Detecting Over Programmed Memory,” filed on Jul. 29, 2003; U.S. Pat. Nos. 6,522,580; and 6,643,188; all four of which are incorporated herein by reference in their entirety.
Some EEPROM and flash memory devices have a floating gate that is used to store two ranges of charges and, therefore, the memory cell can be programmed/erased between two states (an erased state and a programmed state). Such a flash memory device is sometimes referred to as a binary flash memory device.
A multi-state flash memory device is implemented by identifying multiple distinct allowed/valid programmed threshold voltage ranges separated by forbidden ranges. Each distinct threshold voltage range corresponds to a predetermined value for the set of data bits encoded in the memory device.
Shifts in the apparent charge stored on a floating gate can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates. This phenomena is described in U.S. Pat. No. 5,867,429, which is incorporated herein by reference in its entirety. The problem occurs most pronouncedly between sets of adjacent memory cells that have been programmed at different times. For example, a first memory cell is programmed to add a level of charge to its floating gate that corresponds to one set of data. Subsequently, one or more adjacent memory cells are programmed to add a level of charge to their floating gates that correspond to a second set of data. After the one or more of the adjacent memory cells are programmed, the charge level read from the first memory cell appears to be different than programmed because of the effect of the charge on the adjacent memory cells being coupled to the first memory cell. The coupling from adjacent memory cells can shift the apparent charge level being read a sufficient amount to lead to an erroneous reading of the data stored.
The effect of the floating gate to floating gate coupling is of greater concern for multi-state devices because multi-state devices typically have smaller threshold voltage margins between states than that of binary devices, in addition to storing greater amounts of charge. Additionally, the difference in charge stored between the lowest state and the highest state of a multi-state device is likely to be greater than the difference in charge stored between the erased and programmed states of a binary memory device. The magnitude of the voltage coupled between adjacent floating gates is based on the magnitude of charge stored on the adjacent floating gates.
As memory cells continue to shrink in size, the associated reduction in space between word lines as well as between bit lines will also increase the coupling between adjacent floating gates. Furthermore, the natural programming and erase distributions of threshold voltages are expected to increase due to short channel effects, greater oxide thickness/coupling ratio variations and more channel dopant fluctuations. This will dictate increased the separation between the lowest state and the highest state of multi-state memory devices. Also, as more bits of data are encoded in a multi-state memory device, more states are needed; therefore, there will be a greater separation between the lowest state and the highest state. Increasing the separation between the lowest state and the highest state of multi-state memory devices may increase the coupled voltage between adjacent floating gates.
Thus, there is a need to reduce the effect of coupling between floating gates.